`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/02/24 01:41:51
// Design Name: 
// Module Name: float_mul_div_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module float_mul_tb();

  // 定义时钟信号
  reg clk;

  // 定义输入信号
  reg a_tvalid;
  reg [31:0] a_tdata;
  reg b_tvalid;
  reg [31:0] b_tdata;
  reg mul_result_tready;

  // 定义输出信号
  wire mul_result_tvalid;
  wire [31:0] mul_result_tdata;

  // 实例化被测模块
float_mul u1_float_mul(
    .clk(clk),
    .a_tvalid(a_tvalid),
    .a_tdata(a_tdata),
    .b_tvalid(b_tvalid),
    .b_tdata(b_tdata),
    .mul_result_tready(mul_result_tready),
    .mul_result_tvalid(mul_result_tvalid),
    .mul_result_tdata(mul_result_tdata)
  );

  // 初始化时钟
  initial begin
    clk = 0;
    forever
    #5 clk = ~clk;
  end

  // 初始化输入数据
  initial begin
    a_tvalid = 1;
    a_tdata<=32'b0100_0000_0111_1111_0010_1011_0000_0010;    //3.987
    b_tvalid<=1'b1;
    b_tdata<=32'b0100_0000_1000_0110_0111_1110_1111_1010;    //4.203
    mul_result_tready = 1;
  end


endmodule